A charge transfer device represented by a CCD (Charge Coupled Device) and a buried channel-type MOS transistor (a depletion-type MOS transistor) has a structure where an electrode is disposed on a diffusion layer on a surface of a silicon substrate via an insulation layer (for example, see Patent documents 1 to 3). The description below will refer to the figures.
FIG. 9 is a view showing a conventional charge transfer device. FIG. 9A is a cross-sectional view schematically showing a structure of the conventional charge transfer device, FIG. 9B is a view showing an impurity density distribution of the charge transfer device shown in FIG. 9A, and FIG. 9C is a view showing an electric potential distribution of the charge transfer device shown in FIG. 9A.
Each of the distribution diagrams shown in FIGS. 9B and 9C is taken on line Y-Y′ of FIG. 9A. Points A, B and C in FIGS. 9B and 9C correspond to points A, B and C on line Y-Y′ shown in FIG. 9A, respectively. FIG. 9C shows an electric potential distribution when applying a voltage to a transfer electrode 42b described below and depleting a second semiconductor region 45 underneath the transfer electrode 42b. 
The charge transfer device shown in FIG. 9A is a buried channel CCD. As shown in FIG. 9A, the charge transfer device is provided with a semiconductor substrate 41, transfer electrodes 42a to 42c and an insulation layer (a silicon oxide film or the like) 43. The transfer electrodes 42a to 42c are disposed on the semiconductor substrate 41 via the insulation layer 43.
In the semiconductor substrate 41, a p-type first semiconductor region (a p-layer) 44 is formed in a position where the transfer electrodes 42a to 42c overlap the semiconductor substrate 41 in its thickness direction. Moreover, a n-type second semiconductor region (a n-layer) 45 is formed on the first semiconductor region 44. The second semiconductor region 45 is a channel portion of the CCD. Further, pulse voltages are applied to the transfer electrodes 42a to 42c via terminals 46a to 46c, thereby transferring an electric charge.
FIG. 10 is a view showing a conventional buried channel-type MOS transistor. FIG. 10A is a cross-sectional view schematically showing a structure of the conventional buried channel-type MOS transistor, and FIG. 10B is a view showing an electric potential distribution of the buried channel-type MOS transistor shown in FIG. 10A.
Moreover, the electric potential distribution shown in FIG. 10B is taken on line Z-Z′ of FIG. 10A. Points A, B and C in FIG. 10B correspond to points A, B and C on line Z-Z′ shown in FIG. 10A, respectively.
As shown in FIG. 10, the buried channel-type MOS transistor is formed in the semiconductor substrate 51. In the example shown in FIG. 10, the semiconductor substrate 51 is p-type, and a p-type semiconductor region 54 is formed in the semiconductor substrate 51. Moreover, in the semiconductor substrate 51, n-type semiconductor regions 56 and 57 serving as a source or a drain are formed. Further, between the semiconductor region 56 and the semiconductor region 57, a n-type semiconductor region 55 serving as a channel portion is formed so that a channel is formed even when the voltage applied to a gate is 0 V. The n-type semiconductor region 55 serving as the channel portion has a density lower than those of the n-type semiconductor regions 56 and 57 serving as the source or the drain. Moreover, on the n-type semiconductor region 55, a gate electrode 52 is provided via the gate insulation film 53.    Patent document 1: JP 2001-230403 A (FIG. 2)    Patent document 2: JP 7(1995)-161978 A    Patent document 3: JP 7(1995)-326739 A